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A floating-point FFT Twiddle factor implementation based on adaptive angle recoding CORDIC
Proceedings - 2017 International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SigTelCom 2016 Số , năm 2017 (Tập , trang 21-26)
DOI: 10.1109/SIGTELCOM.2017.7849789
Tài liệu thuộc danh mục: ISI, Scopus
Conference Paper
English
Từ khóa: Digital arithmetic; Fast Fourier transforms; Field programmable gate arrays (FPGA); Logic Synthesis; Mean square error; Floating points; FPGA implementations; Maximum error; Maximum frequency; Resources utilizations; Single precision; Standard cell; Twiddle factor; Signal processing
Tóm tắt tiếng anh
In this paper, a single-precision floating-point FFT Twiddle Factor (TF) implementation is proposed. The architecture is based on Adaptive Angle Recoding CORDIC (AARC) algorithm. The TF design is built and verified on Altera Stratix IV FPGA chip and 65nm SOTB synthesis. The FPGA implementation has 103.9 MHz maximum frequency, throughput result of 16.966 Mega-Sample per second (MSps), and resources utilization of 7, 747 ALUTs and 625 registers. On the other hand, the SOTB synthesis has 16, 858 standard cells on an area of 86, 718um2, 166 MHz maximum frequency, and the speed of 27.107 MSps. The accuracy results are 1.133E - 10 Mean-Square-Error (MSE) and about 26 part-per-million (ppm) maximum error-ratio. � 2017 IEEE.
