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A high-speed unsigned 32-bit multiplier based on booth-encoder and wallace-tree modifications
International Conference on Advanced Technologies for Communications Số , năm 2015 (Tập 2015-February, trang 739-744)
ISSN: 21621039
ISSN: 21621039
DOI: 10.1109/ATC.2014.7043485
Tài liệu thuộc danh mục: Scopus
Conference Paper
English
Từ khóa: Adders; Forestry; Frequency multiplying circuits; Image processing; Signal encoding; Carry look-ahead adder; High Speed; High speed implementation; Maximum frequency; Proposed architectures; Radix-4; Timing performance; Wallace tree; Integrated circuit design; Design; Trees
Tóm tắt tiếng anh
The delay of the multiplier plays a critical role in many high-speed implementations and processors such as RISC, DSP, and image processing cores, etc. In this paper, a design of unsigned 32-bit multiplier is proposed, aiming to achieve the best timing performance with an appropriate area. The proposed architecture consists of a modified Radix-4 Booth encoder, a modified Wallace Tree adder, and a Carry Look Ahead adder. The design has been verified successfully on DE2-115 and then synthesized to ASIC implementation. The FPGA-based experimental result shows that it has the resources of 1788 ALUTs. The synthesized result occupies an area of 58.28 mm2 with 4.13 ns total delay (i.e. 242.13MHz maximum frequency). © 2014 IEEE.
