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A high throughput pipelined hardware architecture for tag sorting in packet fair queuing schedulers
2015 International Conference on Computing, Management and Telecommunications, ComManTel 2015 Số , năm 2016 (Tập , trang 41-45)
DOI: 10.1109/ComManTel.2015.7394257
Tài liệu thuộc danh mục: Scopus
Conference Paper
English
Từ khóa: Clocks; Field programmable gate arrays (FPGA); Network architecture; Reconfigurable hardware; Sorting; Throughput; Clock frequency; Critical steps; FPGA technology; High throughput; Network systems; Packet scheduler; Pipelined architecture; Pipelined hardware; Quality of service
Tóm tắt tiếng anh
In a timestamp-base packet scheduler, which is an important part of Quality of Service (QoS) enabled network systems, Tag Sorting is the most critical step. This paper presents a high throughput pipelined architecture for Tag Sorting targeting FPGA technology. Our implementation results on Xilinx Virtex II pro 50 chip have shown that our design can run at a maximum clock frequency of 216 MHz and process one tag every 2 clock cycles, thus provides 108 million tags per second throughput and can support 100 Gbps line speeds. � 2015 IEEE.
