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A low-resource low-latency hybrid adaptive CORDIC in 180-nm CMOS technology
IEEE Region 10 Annual International Conference, Proceedings/TENCON Số , năm 2016 (Tập 2016-January, trang -)
ISSN: 21593442
ISSN: 21593442
DOI: 10.1109/TENCON.2015.7372987
Tài liệu thuộc danh mục: ISI, Scopus
Conference Paper
English
Từ khóa: Adaptive algorithms; CMOS integrated circuits; Digital computers; Co-ordinate rotation digital computers; CORDIC algorithms; FPGA implementations; Hardware architecture; Hybrid architectures; Parallel and pipeline; Resource consumption; Resource sharing; Reconfigurable hardware
Tóm tắt tiếng anh
In this paper, a low-resource low-latency hybrid adaptive COordinate Rotation DIgital Computer (HA-CORDIC) is implemented both in FPGA and 180-nm CMOS technology. The adaptive algorithm reduces around 50% iterations in comparison with the conventional CORDIC algorithm. The hybrid architecture together with resource sharing, parallel and pipeline processing are utilized in HA-CORDIC implementation. In FPGA implementation, the results show that the proposed system can operate at 108.15-MHz frequency, with 716 LUTs and 473 registers resource consumption. In CMOS implementation, the hardware architecture costs 10,299 cells with 0.41 mm2 area and fully operates at 50-MHz frequency. � 2015 IEEE.
