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A proposed RISC instruction set architecture for the MAC unit of 32-bit VLIW DSP processor core
2014 International Conference on Computing, Management and Telecommunications, ComManTel 2014 Số , năm 2014 (Tập , trang 170-175)
DOI: 10.1109/ComManTel.2014.6825599
Tài liệu thuộc danh mục: Scopus
Conference Paper
English
Từ khóa: Digital signal processors; Reduced instruction set computing; Signal processing; Accumulate; Common operations; Computational units; Instruction set architecture; Modelsim software; Multiply; Specific hardware; VLIW; Very long instruction word architecture
Tóm tắt tiếng anh
Multiplier-accumulator is a specific hardware unit that performs a common operation - computing the product of two numbers and adding that product to an accumulator. Especially, in digital signal processing applications which consist of a large number of convolution operations, the emergence of MAC unit contributes greatly to the high performance of the systems. This work is about an implementation for a specific MAC unit based on the proposed RISC instruction set architecture (ISA) of 32-bit VLIW Fixed-point DSP processor core presented in our previous work. The computational unit is designed to be flexible for 32-bit/16-bit/8-bit data computations. The implementation is verified to function correctly not only in Modelsim software but also on Altera Cyclone II (2C35) FPGA board. � 2014 IEEE.
