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A reconfiguration solution for CMOS frequency synthesizers in cognitive radios
International Conference on Advanced Technologies for Communications Số , năm 2016 (Tập 2016-January, trang 428-433)
ISSN: 21621039
ISSN: 21621039
DOI: 10.1109/ATC.2015.7388365
Tài liệu thuộc danh mục: Scopus
Conference Paper
English
Từ khóa: CMOS integrated circuits; Energy conservation; Frequency synthesizers; Locks (fasteners); Phase locked loops; Radio systems; Tuning; Direct digital synthesizer; Fast-locking; Frequency-tuning; Hybrid architectures; Phase Locked Loop (PLL); Reference frequency; Software algorithms; Spectrum sensing; Cognitive radio
Tóm tắt tiếng anh
This article proposes a reconfiguration solution for CMOS frequency synthesizer with a hybrid architecture which is a combination of a Direct Digital Synthesizer (DDS) and a Phase Locked Loop (PLL). The DDS is implemented in FPGA platform functioning a reference frequency to the PLL. The PLL is designed using CMOS technology, being reconfigurable to accelerate tuning speed. Instead of employing a hardware-based lock detector, a software algorithm is used to determine the switching time and to optimize the frequency tuning speed, consuming energy or limited pick power. This PLL is used in cognitive radio for spectrum sensing function. � 2015 IEEE.
