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A Scalable FPGA-based Floating-Point Gaussian Filtering Architecture
Proceedings - 2017 International Conference on Advanced Computing and Applications, ACOMP 2017 Số , năm 2018 (Tập , trang 111-116)
ISSN: 137466
ISSN: 137466
DOI: 10.1109/ACOMP.2017.27
Tài liệu thuộc danh mục: Scopus
Proc. - Int. Conf. Adv. Comput. Appl., ACOMP
English
Từ khóa: Digital arithmetic; Field programmable gate arrays (FPGA); Gaussian distribution; Pulse shaping circuits; Floating points; Functional units; Gaussian filtering; Hardware architecture; Improve performance; Novel architecture; Pipeline modeling; Scalable; Computer architecture
Tóm tắt tiếng anh
This paper proposes a novel architecture for a scalable FPGA-based floating-point Gaussian filtering core. The core not only is able to accept floating-point kernels but also allows the kernels to be modified in both size and values at runtime. The proposed floating-point Gaussian filtering core is described with Verilog-HDL and is able to implement on various FPGA families. We schedule the operations of functional units inside the core in a pipeline model to improve performance. The core can be used for a 1D or a 2D Gaussian filtering with a simple wrapper. We conduct multiple experiments with various FPGA families. Experimental results show that our core can work at up to 224 MHz when implemented on a Xilinx Virtex 7 xc7vx485 device. Using this device, our core is able to perform a 2D Gaussian filtering for 40 or 11 7201280 images per second with a 3 3 or a 11 11 floating-point kernel, respectively. � 2017 IEEE.
