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A scalable network-on-chip based neural network implementation on FPGAs
RIVF 2019 - Proceedings: 2019 IEEE-RIVF International Conference on Computing and Communication Technologies Số , năm 2019 (Tập , trang -)
DOI: 10.1109/RIVF.2019.8713613
Tài liệu thuộc danh mục: ISI, Scopus
English
English
Từ khóa: Character recognition; Field programmable gate arrays (FPGA); Integrated circuit interconnects; MATLAB; Network layers; Network-on-chip; Neural networks; Servers; Handwritten digit recognition; Hardware implementations; Multiple processing; Network-on-chip(NoC); Scalable networks; Scalable performance; System scalability; Integrated circuit design
Tóm tắt tiếng anh
This paper presents a feed-forward neural network implementation using a network on chip (NoC) on a field-programmable gate array (FPGA). The design is intended for large neural networks with hundreds of neurons in each layer. It is one of the first publications that fully realizes a large neural network using NoC-based communication. A dedicated NoC is implemented to handle many interconnections among neurons. The design uses multiple processing elements (PE) to exploit the parallelism available in neural network layers. Different PE configurations are implemented and evaluated for area, power consumption and performance. Implementation and experimental results for a handwritten digit recognition system show that using a large neural network with NoC interconnect allows system scalability with scalable performance. The design achieves the maximum performance of 1339 FPOPs/cycle on a Xilinx Virtex-7 XC7VX485T FPGA. Its latency is 18-times faster than an Intel i7-3.4 GHz CPU running Matlab for this application. � 2019 IEEE.
