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An efficient FPGA implementation of the advanced encryption standard algorithm
2012 IEEE RIVF International Conference on Computing and Communication Technologies, Research, Innovation, and Vision for the Future, RIVF 2012 Số , năm 2012 (Tập , trang -)
DOI: 10.1109/rivf.2012.6169845
Tài liệu thuộc danh mục: Scopus
Conference Paper
English
Từ khóa: Advanced Encryption Standard algorithms; AES; Block ciphers; Decryption; FPGA implementations; FPGA-based implementation; High throughput; Key sizes; Looping approaches; Low latency; Low-complexity architecture; Rijndael; Algorithms; Data privacy; Field programmable gate arrays (FPGA); Innovation; Cryptography
Tóm tắt tiếng anh
A proposed FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is presented in this paper. This implementation is compared with other works to show the efficiency. The design uses an iterative looping approach with block and key size of 128 bits, lookup table implementation of S-box. This gives low complexity architecture and easily achieves low latency as well as high throughput. Simulation results, performance results are presented and compared with previous reported designs. �2012 IEEE.
