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An efficient hardware logarithm generator with modified quasi-symmetrical approach for digital signal processing
International Journal of Electrical and Computer Engineering Số 5, năm 2020 (Tập 10, trang 4671-4678)
DOI: 10.11591/ijece.v10i5.pp4671-4678
Tài liệu thuộc danh mục: Scopus
English
English
Tóm tắt tiếng anh
This paper presents a low-error, low-area FPGA-based hardware logarithm generator for digital signal processing systems which require high-speed, real time logarithm operations. The proposed logarithm generator employs the modified quasi-symmetrical approach for an efficient hardware implementation. The error analysis and implementation results are also presented and discussed. The achieved results show that the proposed approach can reduce the approximation error and hardware area compared with traditional methods. Copyright 2020 Institute of Advanced Engineering and Science. All rights reserved.