An efficient runtime adaptable floating-point Gaussian filtering core

With the fast increasingly use of image and video processing in many aspects, the requirements for high performance and high-quality systems lead to the use of reconfigurable computing to accelerate traditional image processing platforms. In this work, an efficient runtime adaptable floatingpoint Gaussian filtering core is proposed to achieve not only high performance and quality but also kernel runtime adaptability. The architecture allows both filtering kernel size and values to be redefined on-the-fly. Moreover, the core can process up to one pixel per cycle with a 1D Gaussian filtering. The core is developed with Verilog-HDL and can be built on various FPGA families. Experimental results with multiple images at different resolutions show that the core is able to perform a 2D Gaussian filtering for 48 1080 � 1920-pixel or 313 512 � 512-pixel images per second with an 11 � 11 floating-point kernel. � 2017 IEEE.