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An optimized hardware design of integer motion estimation HEVC for encoding 8K video
2017 4th NAFOSTED Conference on Information and Computer Science, NICS 2017 - Proceedings Số , năm 2017 (Tập 2017-January, trang 319-324)
DOI: 10.1109/NAFOSTED.2017.8108085
Tài liệu thuộc danh mục: Scopus
Conference Paper
English
Từ khóa: Image compression; Integer programming; Motion estimation; Signal encoding; 8K video; Frames per seconds; H.265; HEVC; High Efficiency Video Coding (HEVC); Integer motion estimation; Optimized architectures; Video compression standards; Video signal processing
Tóm tắt tiếng anh
High Efficiency Video Coding (HEVC) is the new video compression standard. A novel optimized architecture of Integer Motion Estimation (IME) for HEVC processing 8K video is presented in this paper. This architecture achieves 8K (7680�4320) video in real time at 43 fps (frames per second) with a frequency of 142 MHz and a latency of 402 clock cycles. The proposed design has been synthesized and simulated by Xilinx ISE 14.7 using Virtex-7 28nm technology. Up to now, this is the first IME design reaching 8K video requirements which can be implemented in a FPGA kit in real time. � 2017 IEEE.
