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Deep neural network accelerator based on FPGA
2017 4th NAFOSTED Conference on Information and Computer Science, NICS 2017 - Proceedings Số , năm 2017 (Tập 2017-January, trang 254-257)
DOI: 10.1109/NAFOSTED.2017.8108073
Tài liệu thuộc danh mục: Scopus
Conference Paper
English
Từ khóa: Character recognition; Computer architecture; Digital arithmetic; Feedforward neural networks; Field programmable gate arrays (FPGA); Learning systems; Network architecture; Reconfigurable architectures; Efficient architecture; Floating points; Handwritten digit recognition; Hardware realization; MNIST; Performance evaluations; Precision floating point; Reconfigurable computing; Deep neural networks
Tóm tắt tiếng anh
In this work, we propose an efficient architecture for the hardware realization of deep neural networks on reconfigurable computing platforms like FPGA. The proposed neural network architecture employs only one single physical computing layer to perform the whole computational fabric of fully-connected feedforward deep neural networks with customizable number of layers, number of neurons per layer and number of inputs. The inputs, weights and outputs of the network are represented in 16-bit half-precision floating-point number format. The network weights are hard-coded using onchip memory of FPGA devices, allowing for very fast computation. For performance evaluation, the handwritten digit recognition application with MNIST database is performed, which reported a recognition rate of 97.20% and a peak performance of 15.81 kFPS when using a deep neural network of size 784-40-40-10 on the Xilinx Virtex-5 XC5VLX-110T device. When implementing a deep neural network of size 784-126-126- 10 for MNIST database on the Xilinx ZynQ-7000 XC7Z045 device, the recognition rate is 98.16% and the peak performance is 15.90 kFPS. � 2017 IEEE.
