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Design and Implementation of Signal Processing Unit for Two-Way Relay Node in MIMO-SDM-PNC System
2019 26th International Conference on Telecommunications, ICT 2019 Số , năm 2019 (Tập , trang 142-148)
DOI: 10.1109/ICT.2019.8798767
Tài liệu thuộc danh mục: Scopus
English
Từ khóa: Computer hardware description languages; Field programmable gate arrays (FPGA); Integrated circuit design; Logic Synthesis; Mean square error; MIMO systems; Network architecture; Network coding; Network layers; Signal receivers; Space division multiple access; Design and implementations; Minimum mean square error detectors; MMSE; Physical layer network coding (PNC); Processing architectures; Proposed architectures; Signal processing unit; Spatial Division Multiplexing; Computer architecture
Tóm tắt tiếng anh
This paper investigates design and implementation of the signal processing unit for the relay node in a two-way relay multiple-input multiple-output spatial division multiplexing (MIMO-SDM) system using physical-layer network coding (PNC), reffered to as MIMO-SDM-PNC. Based on Field-programmable gate array (FPGA) platform, two processing architectures for zero-forcing (ZF) and minimum mean square error (MMSE) detector are proposed for the relay node. Using the standard pipe-lining and the parallel computing methodologies, a novel architecture is developed in order to achieve low latency and low-Area occupation for FPGA implementation. The proposed architecture has been composed in Verilog language and synthesized on the ISE tool for Xilinx FPGA Virtex 7. Experimental results demonstrate that the proposed design offers high performance in terms of low latency and high throughput. � 2019 IEEE.
