Design framework for FPGA-based hardware accelerators with heterogeneous interconnect

In recent years, several hardware accelerators have been proposed for both embedded and high-performance computing systems. Hardware accelerators nowadays become more popular for improving the performance of modern computing systems such as Machine Learning or Big Data analytics. However, the interconnects in general-purpose hardware accelerators are not well optimized to satisfy the communication demands of an application. In this work, we present an automated approach to design hardware accelerator systems with an efficient hybrid interconnect for hardware kernels driven by the detailed data communication patterns of an application. The heterogeneous interconnect includes an NoC, shared local memory, or both. Based on the quantitative data communication profile, each application is developed with a custom hybrid interconnect to achieve an optimized performance while keeping the hardware resource usage for the interconnect as low as possible. Our experimental results in an embedded system and a high-performance computing system achieve overall application speed-ups by up to 2.87� and 1.54� compared to the baseline systems, respectively. The experimental results also show that the designed systems can reduce hardware resources usage up to 33% for the embedded system and 45% for the high-performance computing system. � 2019 IEEE.