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Design of a low latency network interface using dual buffer for network on chip
2015 International Conference on Computing, Management and Telecommunications, ComManTel 2015 Số , năm 2016 (Tập , trang 205-209)
DOI: 10.1109/ComManTel.2015.7394288
Tài liệu thuộc danh mục: Scopus
Conference Paper
English
Từ khóa: Complex networks; Design; Field programmable gate arrays (FPGA); Interfaces (computer); Network architecture; Network-on-chip; Programmable logic controllers; Routers; Servers; System-on-chip; VLSI circuits; Latency; Low-latency networks; Network interface architecture; Network-on-chip(NoC); Networkinterface; Processing resources; Systems on chips; Writing process; Integrated circuit design
Tóm tắt tiếng anh
Recently, Network-on-Chip (NoC) paradigm has been known as a promising solution for complex Systems-on- Chip (SoC) design. A network interface is a significant part of a NoC. The network interface operates like a bridge between processing resources and network routers. This paper presents a new network interface design using parallel writing and reading buffers. The network interface architecture is modeled using Verilog HDL and implemented targeting Xilinx Virtex-6 board. The experimental results prove that our network interface design can obtain stability, reduce average latency of the packet up to 25.1 % and have a higher speed compared to an architecture that uses one normal FIFO buffer for both reading and writing processes. � 2015 IEEE.
