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Double SHA-256 Hardware Architecture with Compact Message Expander for Bitcoin Mining
IEEE Access Số , năm 2020 (Tập 8, trang 139634-139646)
DOI: 10.1109/ACCESS.2020.3012581
Tài liệu thuộc danh mục: ISI, Scopus
English
Từ khóa: Bitcoin; CMOS integrated circuits; Electric power utilization; System-on-chip; Conventional approach; Hardware architecture; Hardware platform; Low-power consumption; Lowpower hardware; Processing rates; Proposed architectures; Resource sharing; Network architecture
Tóm tắt tiếng anh
In the Bitcoin network, computing double SHA-256 values consumes most of the network energy. Therefore, reducing the power consumption and increasing the processing rate for the double SHA-256 algorithm is currently an important research trend. In this paper, we propose a high-data-rate low-power hardware architecture named the compact message expander (CME) double SHA-256. The CME double SHA-256 architecture combines resource sharing and fully unrolled datapath technologies to achieve both a high data rate and low power consumption. Notably, the CME algorithm utilizes the double SHA-256 input data characteristics to further reduce the hardware cost and power consumption. A review of the literature shows that the CME algorithm eliminates at least 9.68% of the 32-bit XOR gates, 16.49% of the 32-bit adders, and 16.79% of the registers required to calculate double SHA-256. We synthesized and laid out the CME double SHA-256 using CMOS 0.18~\mu m technology. The hardware cost of the synthesized circuit is approximately 13.88% less than that of the conventional approach. The chip layout size is 5.9 mm \times 5.9 mm , and the correctness of the circuit was verified on a real hardware platform (ZCU 102). The throughput of the proposed architecture is 61.44 Gbps on an ASIC with Rohm 180nm CMOS standard cell library and 340 Gbps on a FinFET FPGA 16nm Zynq UltraScale+ MPSoC ZCU102. � 2013 IEEE.
