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FPGA-based frequent items counting using matrix of equality comparators
Midwest Symposium on Circuits and Systems Số , năm 2017 (Tập 2017-August, trang 285-288)
ISSN: 15483746
ISSN: 15483746
DOI: 10.1109/MWSCAS.2017.8052916
Tài liệu thuộc danh mục: ISI, Scopus
Conference Paper
English
Từ khóa: Application programs; Clocks; Comparator circuits; Comparators (optical); Field programmable gate arrays (FPGA); Average throughput; Clock frequency; FPGA-based implementation; Proposed architectures; System-on-chip
Tóm tắt tiếng anh
In this paper, an FPGA-based implementation of Frequent Items Counting is proposed. The architecture deploys the equality comparator matrix for comparing the input items with themselves to count them instantly within a single operating clock. The proposed architecture is applied to the case of the 8-bit item. That means 256 different types of items in total. The system is built and verified on the Altera Arria V SoC Development Kit. The experimental results show that the implementation can perform on the maximum clock frequency of 40.85 MHz and requires 51,094 ALUTs and 8,417 registers, which is about 29% of the FPGA's resources. The average throughput performance achieves 1,280 millions items per second, which is about 50 times faster than that of the software-based application at the same setting. � 2017 IEEE.
