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FPGA design and implementation of a real-time stereo vision system
IEEE Transactions on Circuits and Systems for Video Technology Số 1, năm 2010 (Tập 20, trang 15-26)
ISSN: 10518215
ISSN: 10518215
DOI: 10.1109/TCSVT.2009.2026831
Tài liệu thuộc danh mục: Scopus
Article
English
Từ khóa: Basic mechanism; Conventional computers; Data access; Dedicated hardware; FPGA design; Fully pipelined; Hardware implementations; Human eye; Integrated circuit design; Integrated circuit designs; Post processing; Real time stereo; Realtime processing; Software program; Stereo matching; Stereo vision system; Subpixel accuracy; Computational complexity; Computer hardware; Field programmable gate arrays (FPGA); Hardware; Integrated circuit manufacture; Integrated circuits; Logic gates; Signal processing; Signal receivers; Video recording; Video signal processing; Stereo vision
Tóm tắt tiếng anh
Stereo vision is a well-known ranging method because it resembles the basic mechanism of the human eye. However, the computational complexity and large amount of data access make real-time processing of stereo vision challenging because of the inherent instruction cycle delay within conventional computers. In order to solve this problem, the past 20 years of research have focused on the use of dedicated hardware architecture for stereo vision. This paper proposes a fully pipelined stereo vision system providing a dense disparity image with additional sub-pixel accuracy in real-time. The entire stereo vision process, such as rectification, stereo matching, and post-processing, is realized using a single field programmable gate array (FPGA) without the necessity of any external devices. The hardware implementation is more than 230 times faster when compared to a software program operating on a conventional computer, and shows stronger performance over previous hardware-related studies. � 2010 IEEE.
