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FPGA implementation of MIMO OFDM eigenbeam-space division multiplexing systems for future wireless communications networks

Hieu N.T. DCSELAB, University of Technology, Viet Nam|
Ogawa Y. | Thanh V.D. Hokkaido University, Japan| Phu B.H. University of Technology, Viet Nam|

IEEE Vehicular Technology Conference Số , năm 2013 (Tập , trang -)

ISSN: 15502252

ISSN: 15502252

DOI: 10.1109/VTCFall.2013.6692208

Tài liệu thuộc danh mục: Scopus

Conference Paper

English

Từ khóa: Computer based simulation; Design and implementations; E-SDM; Eigenbeam-space division multiplexing; FPGA implementations; Hardware design; High-speed wireless communication; Wireless communications networks; Communication systems; Computer aided analysis; Design; Digital signal processing; Field programmable gate arrays (FPGA); Gain control; Hardware; MIMO systems; Multiplexing equipment; Orthogonal frequency division multiplexing; Wireless telecommunication systems; Space division multiple access
Tóm tắt tiếng anh
It is well known that Multiple-Input Multiple-Output Orthogonal Frequency Division Multiplexing Eigenbeam-Space Division Multiplexing systems, namely MIMO-OFDM E-SDM systems, are considered a promising candidate for future highspeed wireless communication networks because of having the maximal channel capacity and good communications reliability. In the systems, orthogonal transmission beams are formed between transmit and receive sides; and also optimal transmit input data are adaptively allocated. In addition, a simple detection can be used at a receiver to totally eliminate sub-stream interference. Although many papers have studied and evaluated the systems based on theoretical analyses and/or computer-based simulations, there have not been papers that investigated the systems based on their design and implementation on FPGA hardware. The main contribution of this paper is to present our own design and implementation of 2x2 and 2x3 MIMO-OFDM ESDM systems on FPGA Altera Stratix DSP Development KIT using Verilog HDL. The bit-error rate performance of these systems is evaluated and shown that our design is successful. In the paper, we also show the consumption of FPGA elements for our design of the systems. Copyright � 2013 by the Institute of Electrical and Electronic Engineers, Inc.

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