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Hardware Implementation of a MIMO Channel Emulator for high speed WLAN 802.11ac
NICS 2018 - Proceedings of 2018 5th NAFOSTED Conference on Information and Computer Science Số , năm 2019 (Tập , trang 183-188)
DOI: 10.1109/NICS.2018.8606847
Tài liệu thuộc danh mục: Scopus
Conference Paper
English
Từ khóa: Computer hardware; Field programmable gate arrays (FPGA); Parallel architectures; Wireless local area networks (WLAN); Hardware implementations; High sampling rates; High Speed; IEEE 802.11ac; Maximum frequency; MIMO channel; Sampling rates; Software calculations; IEEE Standards
Tóm tắt tiếng anh
In this paper, we present a hardware implementation of a 4x4 MIMO channel emulator for WLAN 802.11ac. High sampling rate and scalable number of taps are targets of MIMO channel emulator. We propose a design of MIMO channel emulator with parallel architecture. We also reduce the number of hardware calculations by using many pre-calculated parameters from software calculations. An implementation on Xilinx Virtex-7 V2000T occupies 929142 slice registers about 38% of the available configurable slice registers and 349416 slice LUTs about 29% FPGA's slice LUTs. The maximum frequency of our emulator is 305.181 MHz, which means it can respond the sampling rate of 802.11ac baseband IQ signal. � 2018 IEEE.
