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Hardware implementation of cyclic codes error correction on FPGA
NICS 2016 - Proceedings of 2016 3rd National Foundation for Science and Technology Development Conference on Information and Computer Science Số , năm 2016 (Tập , trang 97-100)
ISSN: 124536
ISSN: 124536
DOI: 10.1109/NICS.2016.7725675
Tài liệu thuộc danh mục: Scopus
NICS - Proc. Natl. Found. Sci. Technol. Dev. Conf. Inf. Comput. Sci.
English
Từ khóa: Encoding (symbols); Error correction; Field programmable gate arrays (FPGA); Hardware; Table lookup; cyclic; Decoding methods; Decoding system; encode; Hardware implementations; Look up table; Look up table methods; Number of cycles; Decoding
Tóm tắt tiếng anh
This paper designs and implements a codec system using the Cyclic code on FPGA. The encoding system was based on the principle of dividing circuits and the decoding system was based on the principle of the Meggitt decoder. This work proposes the look-up table (LUT) method for the decoding system. The implementation results from FPGA show that the proposed decoding method has exactly resulted. In addition, the proposed cyclic decoder core using the look-up table method has lower resource and number of cycles compared to the cyclic decoder core using the Meggitt method. � 2016 IEEE.
