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Hardware implementation of MFCC feature extraction for speech recognition on FPGA
Advances in Intelligent Systems and Computing Số , năm 2017 (Tập 538 AISC, trang 248-254)
ISSN: 9783319490724
ISSN: 9783319490724
DOI: 10.1007/978-3-319-49073-1_27
Tài liệu thuộc danh mục: Scopus
Final
English
Từ khóa: Feature extraction; Field programmable gate arrays (FPGA); Hardware; Hardware implementations; IP core; Mel-frequency cepstral coefficients; Resource usage; Speech recognition
Tóm tắt tiếng anh
In this paper, an FPGA-based Mel Frequency Cepstral Coefficient (MFCC) IP core for speech recognition is presented. The implementation results on FPGA show that the proposed MFCC core achieves higher resource usage efficiency compared with other designs. Springer International Publishing AG 2017.