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Hardware/software co-design of power level difference based noise cancellation
International Conference on Advanced Technologies for Communications Số , năm 2016 (Tập 2016-January, trang 616-621)
ISSN: 21621039
ISSN: 21621039
DOI: 10.1109/ATC.2015.7388404
Tài liệu thuộc danh mục: Scopus
Conference Paper
English
Từ khóa: Computer hardware description languages; Field programmable gate arrays (FPGA); Integrated circuit design; Programmable logic controllers; System-on-chip; Complex control; Hardware resources; Input datas; Noise cancellation; Noise cancelling; Power level differences; Real time; Xilinx FPGA; Hardware-software codesign
Tóm tắt tiếng anh
In this paper, the Power Level Difference (PLD)-based noise cancelling algorithm is implemented in a Xilinx FPGA SoC using hardware/software co-design methodology. Thanks to the hardware/software co-design, the complex control part of the algorithm can be fast deployed in software meanwhile the computational part is effectively implemented in hardware. Therefore, the system can not only process the real-time input data but also consumes few hardware resource. � 2015 IEEE.
