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High speed SAD architecture for variable block size motion estimation in HEVC encoder
2016 IEEE 6th International Conference on Communications and Electronics, IEEE ICCE 2016 Số , năm 2016 (Tập , trang 195-198)
ISSN: 123684
ISSN: 123684
DOI: 10.1109/CCE.2016.7562635
Tài liệu thuộc danh mục: ISI, Scopus
IEEE Int. Conf. Commun. Electron., IEEE ICCE
English
Từ khóa: Architecture; Hardware; Image coding; Reconfigurable hardware; Video signal processing; HEVC; HEVC Encoder; Integer motion estimation; Proposed architectures; Real-time application; Sum of absolute differences; Variable block size; Variable block-size motion estimation; Motion estimation
Tóm tắt tiếng anh
Motion Estimation (ME) is the most time-consuming process in High Efficient Video Coding (HEVC) encoder. The calculation of Sum of Absolute Difference (SAD) between current block and reference block creates the highest computing load in ME process. Moreover, the block size in HEVC can expand up to 64�64 for real time applications, hence the complexity of variable block size SAD calculation increases sharply, and the calculation requires a lot of hardware resources. In this paper, a novel high speed SAD architecture for variable block size ME in HEVC encoder is proposed to reduce the hardware usage as well as the calculation time. The design is integrated with the other parts to make Integer Motion Estimation block as well. The evaluation results of the synthesized system implemented in 65nm Virtex-5 FPGA show that the max frequency of the proposed architecture obtains 190.785 MHz. � 2016 IEEE.
