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High Throughput and Low Cost Memory Architecture for Full Search Integer Motion Estimation in HEVC
International Conference on Advanced Technologies for Communications Số , năm 2018 (Tập 2018-October, trang 174-178)
ISSN: 143867
ISSN: 143867
DOI: 10.1109/ATC.2018.8587488
Tài liệu thuộc danh mục: ISI, Scopus
Int. Conf. Adv. Technol. Commun.
English
Từ khóa: Costs; Memory architecture; Video signal processing; Full search; H.265/HEVC; High throughput; High-efficiency video coding; Integer motion estimation; Maximum frequency; Proposed architectures; Resolution video; Motion estimation
Tóm tắt tiếng anh
The two-dimensional matrix array Integer Motion Estimation (IME) architecture using Full Search Motion Estimation (FSME) algorithm for High Efficiency Video Coding (HEVC) is presented in this paper. This architecture can operate for 4K resolution video at 30 fps with latency as low as 1219 clock cycles, allowing the design working in real-time. The memory required also kept as low as 12.5kB. The proposed architecture can reach maximum frequency of 148.6 MHz using 40 nm or 195.4 MHz in 28nm Virtex-6 FPGA using Xilinx ISE version 13.1. � 2018 IEEE.
