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Implementation of a short word length ternary FIR filter in both FPGA and ASIC
Proceedings - 2018 2nd International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SIGTELCOM 2018 Số , năm 2018 (Tập 2018-January, trang 45-50)
ISSN: 135592
ISSN: 135592
DOI: 10.1109/SIGTELCOM.2018.8325803
Tài liệu thuộc danh mục: ISI, Scopus
Proc. - Int. Conf. Recent Adv. Signal Process., Telecommun. Comput., SIGTELCOM
English
Từ khóa: Application specific integrated circuits; Bandpass filters; Economic and social effects; Field programmable gate arrays (FPGA); Hardware; Integrated circuit design; MATLAB; Modulators; Pipelines; Signal processing; Design and implementations; Hardware efficiency; Hardware resources; ITS applications; Operating frequency; Over-sampling rates; Sigma Delta modulator; Word length; FIR filters
Tóm tắt tiếng anh
Despite the fact that Short Word Length (SWL) technique has been demonstrated to be a new efficient approach for implementing DSP systems, its applications are somehow limited. In this paper, we present the design and implementation of a Sigma-delta modulator based SWL ternary FIR filter. From predefined specifications, the filter was first modelled and simulated in MATLAB then implemented on a commercial FPGA platform and finally synthesized using ASIC method. We created two versions of the design: pipeline and non-pipeline, their performance are compared and discussed going from the operating frequency to the hardware resource usage. Also, to examine the trade-off between hardware efficiency and performance, we also evaluated the design with four different oversampling rates (8, 16, 32, 64). � 2018 IEEE.
