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Implementation of Fractal image compression on FPGA
2012 4th International Conference on Communications and Electronics, ICCE 2012 Số , năm 2012 (Tập , trang 339-344)
DOI: 10.1109/CCE.2012.6315924
Tài liệu thuộc danh mục: Scopus
Conference Paper
English
Từ khóa: Clock rate; Complete system; Compression performance; Fast fractals; FIC; Fisher's method; FPGA boards; Fractal image compression; Gray level image; Lossy techniques; Single chips; SoC; VLSI technology; Field programmable gate arrays (FPGA); Fractals; Image compression; Programmable logic controllers; Digital signal processing
Tóm tắt tiếng anh
Fractal Image Compression (FIC) is known as a lossy technique, which requires a large amount of operations to complete the codification. The development of VLSI technology allows the creation of complete systems inside a single chip likely FPGA, therefore the number of required operations may reduce and data compression becomes increasingly significant for storage and transmission. In this paper, we propose the implementation of a FIC framework on Xilinx Virtex 5 (XUPV5-LX110T) FPGA board, which allows to significantly decrease the elapsing time compared to that implemented in DSP at the same clock rate of 100MHz. The experimental results performed by Fisher's method for a gray level image have verified the possibility to design a SoC for fast fractal coder/decoder with an increased compression performance. � 2012 IEEE.
