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Optimizating power consumption using Multi-bit Flip-Flop technique in Tetris game on FPGA
Proceedings - 2017 International Conference on System Science and Engineering, ICSSE 2017 Số , năm 2017 (Tập , trang 530-533)
DOI: 10.1109/ICSSE.2017.8030930
Tài liệu thuộc danh mục: Scopus
Conference Paper
English
Từ khóa: Clocks; Electric power utilization; Field programmable gate arrays (FPGA); Clock buffer; Low Power; Multi-bits; Power design; Single bit flips; Tetris; Tetris game; Flip flop circuits
Tóm tắt tiếng anh
In this paper, we design Tetris game which can rotate, generate randomly blocks, eliminate rows, and get scores based on FPGA. Multi-bit Flip-flops (MBFF) concept is implemented into a part of Tetris game to save power consumption and clock buffer area. The 2-bit MBFF and 4-bit MBFF technique are compared with the Single-Bit Flip-flop. Results show that Multi-bit Flip-flops technique is very effective and efficient method in lower power designs and saving clock buffers. The low power Tetris game is a successful model for other visual control systems. � 2017 IEEE.
