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Optimizing Convolutional Neural Network Accelerator on Low-Cost FPGA

Vinh Ho Chi Minh City University of Technology, Vietnam National University-Ho Chi Minh, Ho Chi Minh City, Viet Nam|
Dinh Viet (57222103623) | Truong Quang (24722218300); Hai |

Journal of Circuits, Systems and Computers Số 11, năm 2021 (Tập 30, trang -)

ISSN: 2181266

ISSN: 2181266

DOI: 10.1142/S0218126621501930

Tài liệu thuộc danh mục:

Article

English

Từ khóa: Computation theory; Convolution; Costs; Field programmable gate arrays (FPGA); Integrated circuit design; Storms; System-on-chip; Classification tasks; Clock speed; Data reuse; Logic elements; Multiply accumulate; Optimal number; Processing engine; Resource efficiencies; Convolutional neural networks
Tóm tắt tiếng anh
Convolutional neural network (CNN) is one of the most promising algorithms that outweighs other traditional methods in terms of accuracy in classification tasks. However, several CNNs, such as VGG, demand a huge computation in convolutional layers. Many accelerators implemented on powerful FPGAs have been introduced to address the problems. In this paper, we present a VGG-based accelerator which is optimized for a low-cost FPGA. In order to optimize the FPGA resource of logic element and memory, we propose a dedicated input buffer that maximizes the data reuse. In addition, we design a low resource processing engine with the optimal number of Multiply Accumulate (MAC) units. In the experiments, we use VGG16 model for inference to evaluate the performance of our accelerator and achieve a throughput of 38.8GOPS at a clock speed of 150MHz on Intel Cyclone V SX SoC. The experimental results show that our design is better than previous works in terms of resource efficiency. � 2021 World Scientific Publishing Company.

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