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PC and FPGA design for face recognition system using Hidden Markov Model
International Conference on Electronics, Information, and Communications, ICEIC 2016 Số , năm 2016 (Tập , trang -)
ISSN: 123661
ISSN: 123661
DOI: 10.1109/ELINFOCOM.2016.7563024
Tài liệu thuộc danh mục: Scopus
Int. Conf. Electron., Inf., Commun., ICEIC
English
Từ khóa: Field programmable gate arrays (FPGA); Hidden Markov models; Integrated circuit design; Markov processes; Reconfigurable hardware; Singular value decomposition; Face recognition systems; FPGA design; Parallel Computation; Parallel techniques; Recognition process; Training process; Face recognition
Tóm tắt tiếng anh
Face recognition systems play a vital role in many applications including surveillance, biometrics and security. In this work, we present a face recognition system using Hidden Markov Model (HMM) and Singular Value Decompositions proposed by Naimi an Davari in [3]. In this system, we use parallel technique to accelerate the recognition process. Besides, we use reduced HMMs instead of full HMMs to train the system. This will help in reducing the amount of computations required for training process. � 2016 IEEE.
