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Performance enhancement of encryption and authentication IP cores for IPSec based on multiple-core architecture and dynamic partial reconfiguration on FPGA
Proceedings - 2018 2nd International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SIGTELCOM 2018 Số , năm 2018 (Tập 2018-January, trang 126-131)
ISSN: 135592
ISSN: 135592
DOI: 10.1109/SIGTELCOM.2018.8325775
Tài liệu thuộc danh mục: Scopus
Proc. - Int. Conf. Recent Adv. Signal Process., Telecommun. Comput., SIGTELCOM
English
Từ khóa: Authentication; Electric power utilization; Field programmable gate arrays (FPGA); Intellectual property core; Internet protocols; Memory architecture; Real time systems; Reconfigurable hardware; Security systems; Signal processing; Dynamic partial reconfiguration; high performance cryto-system; IPSec; multiple-cores; Performance enhancements; Real-time application; Run time reconfiguration; System throughput; Cryptography
Tóm tắt tiếng anh
In this paper, we propose a Multiple Core architecture and an DMA bus connectivity to increase the processing speed of encryption and authentication cores in high speed IPSec security systems. Dynamic partial reconfiguration technology (DPR) is used to reduce FPGA resources and power consumption on chips. This paper proposes a model for high-speed Multiple-IPSec security systems that meet real-time applications. The system throughput, power consumption, and resources used when applying Multiple-Core and DPR architectures are also calculated. � 2018 IEEE.
