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Real-Time Lossless Compression of Waveforms Using an FPGA

Truong N.M. Osaka University, Osaka, 560-0043, Japan|
Yamamoto K. | Teshima N. | Seiya Y. | Natori H. | Nakatsugawa Y. Osaka City University, Osaka, 558-8585, Japan| Nagao D. Institute for Basic Science (IBS), Daejeon, 34141, South Korea| Ito S. Institute of High Energy Physics, Beijing, 100049, China| Saito M. Okayama University, Okayama, 700-8530, Japan| Igarashi Y. University of Science and Technology, University of da Nang, Da Nang, 550000, Viet Nam| Aoki M. High Energy Accelerator Research Organization (KEK), Ibaraki, 305-0801, Japan|

IEEE Transactions on Nuclear Science Số 9, năm 2018 (Tập 65, trang 2650-2656)

DOI: 10.1109/TNS.2018.2861880

Tài liệu thuộc danh mục: ISI, Scopus

IEEE Trans Nucl Sci

English

Từ khóa: Analog to digital conversion; Bandwidth; Data acquisition; Data compression ratio; Data transfer rates; Field programmable gate arrays (FPGA); Firmware; Logic gates; Real time systems; Analog to digital converters; Data acquisition system; fast analog-to-digitalconverter (FADC); High energy physics experiments; Lossless compression; Lossless data compression; Multi-wire proportional chambers; Programmable gate array; High energy physics
Tóm tắt tiếng anh
High-energy physics experiments must usually handle large transfer rates of experimental data. In particular, in recent years, the amount and speed of data handled in high-energy physics experiments have significantly increased, because signal waveforms from detectors are often recorded without reduction to maximize the flexibility of the offline analysis. To best exploit the available bandwidth of such data acquisition systems with waveform recording, we developed the real-time lossless waveform-compression firmware that is based on a delta-encoding technique. The firmware provides a compression ratio of 34% of the raw data produced, the fast analog-to-digital converter (FADC) boards of our application before transmission to a host computer. The resource consumption of a field-programmable gate array (FPGA) is not large, and a low-cost mid-range FPGA is sufficient to implement this proposed firmware. The firmware has been successfully implemented on an FADC board and was utilized to record signals from multiwire proportional chambers for the DeeMe experiment. In this paper, we present the theory related to the firmware design and its implementation on the FPGA. � 1963-2012 IEEE.

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