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RTL implementation for a specific ALU of the 32-bit VLIW DSP processor core
International Conference on Advanced Technologies for Communications Số , năm 2015 (Tập 2015-February, trang 387-392)
ISSN: 21621039
ISSN: 21621039
DOI: 10.1109/ATC.2014.7043417
Tài liệu thuộc danh mục: Scopus
Conference Paper
English
Từ khóa: Digital signal processing; Digital signal processors; Fourier analysis; Logic circuits; Reduced instruction set computing; Computational units; Data computation; Digital filtering; Digital signal processing algorithms; Gate-level designs; Instruction set architecture; Modelsim software; VLIW; Very long instruction word architecture
Tóm tắt tiếng anh
Digital Signal Processors (DSPs) have shown the great strengths in digital signal processing algorithms such as digital filtering and Fourier analysis. This work is about an implementation for a specific computational unit based on the proposed RISC instruction set architecture (ISA) of 32-bit VLIW Fixed-point DSP processor core presented in our previous work. The computational unit is designedto be flexible for 32-bit/16-bit/8-bit data computations. The implementation is described from top-level to gate-level design and then it is verified to function correctly not only in Modelsim software but also on Altera Cyclone II (2C35) FPGA board. © 2014 IEEE.
