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Self Clock-Gating Scheme for Low Power Basic Logic Element Architecture
Wireless Personal Communications Số 4, năm 2018 (Tập 102, trang 3477-3488)
DOI: 10.1007/s11277-018-5385-2
Tài liệu thuộc danh mục: ISI, Scopus
Wireless Pers Commun
English
Từ khóa: Clocks; Computer circuits; Electronics packaging; Field programmable gate arrays (FPGA); Semiconductor device manufacture; Basic logic elements; Clock gating; Dynamic Power; Field programmable gate array (FPGAs); Leakage reduction techniques; Power delay product; Proposed architectures; Static power reduction; Memory architecture
Tóm tắt tiếng anh
For field programmable gate arrays (FPGAs) to retain their semiconductor market and to be competitive as a choice for portable applications, the FPGA industry must adopt new techniques for dynamic and static power reduction. In this paper, a new scheme called ‘self clock-gating’ is introduced to reduce the dynamic power of basic logic elements. Circuits are designed using 16 nm Berkeley’s Predictive technology model and tanner EDA tool is used for simulation. When we consider the average power, proposed architecture consumes 14% lesser than standard architecture. However, proposed architecture consumes only 6% of static power as that of standard architecture. If we consider the energy (power delay product), with the leakage reduction technique, the power delay product is 0.164 femto joules for the proposed architecture but in standard architecture, it is 0.200 femto joules. © 2018, Springer Science+Business Media, LLC, part of Springer Nature.
