LIÊN KẾT WEBSITE
VLSI design of floating-point twiddle factor using adaptive CORDIC on various iteration limitations
Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018 Số , năm 2018 (Tập , trang 225-232)
ISSN: 142785
ISSN: 142785
DOI: 10.1109/MCSoC2018.2018.00044
Tài liệu thuộc danh mục: Scopus
Proc. - IEEE Int. Symp. Embed. Multicore/Many-Core Syst.-on-Chip, MCSoC
English
Từ khóa: Adaptive algorithms; Digital arithmetic; Digital computers; Embedded systems; Fast Fourier transforms; Field programmable gate arrays (FPGA); Iterative methods; Signal receivers; Silicon compounds; Silicon on insulator technology; VLSI circuits; Application specific; COordinate Rotation DIgital Computer (CORDIC); CORDIC; Floating points; Number of iterations; Thin buried oxides; Twiddle factor; VLSI; Integrated circuit design
Tóm tắt tiếng anh
The design of 32-bit floating-point Fast Fourier Transform (FFT) Twiddle Factor (TF) is proposed in this paper. The architecture was developed based on the adaptive algorithm of COordinate Rotation DIgital Computer (CORDIC). The CORDIC method is a well-known approach for approximating the complex-number multiplication in FFT implementations, also known as TF. An iterative process does the calculations of adaptive CORDIC. Therefore, by limiting the number of iterations, the accuracy performances can be sacrificed for the better outcome of throughput rates. As a result, there are three different FFT TF implementations were presented in this paper. They are TF-4, TF-8, and TF-16 for the design of TF implemented on four, eight, and 16 iteration limitations, respectively. The results of the three implementations were reported on both Field Programmable Gate Array (FPGA) and Application Specific Integrated Chip (ASIC) level. The FPGA results were examined on the Altera Stratix IV development kit, and the ASIC results were reported by the Synopsys tools with the Silicon On Thin Buried-oxide (SOTB) 65nm process library. 2018 IEEE.